The present invention relates to integrated circuits fabricated on semiconductor dies and, more particularly, to a method of selling such circuits that are intended for use in Multi-Chip Packages (MCPs).
FIG. 1 illustrates one prior art method of packaging integrated circuits fabricated on semiconductor dies. Specifically, FIG. 1 is a schematic plan view of the interior of a Single-Chip Package (SCP) 10. An integrated circuit 12 including a plurality of bonding pads 16 is fabricated on a semiconductor die 14. Semiconductor die 14 is mounted on a substrate 18 on which are formed electrically conductive traces 20 connected to pins 22. Each bonding pad 16 is electrically connected to a respective trace 20 by a wire bond 24. Pins 22 provide electrical connection of integrated circuit 12 to other components of a larger electronic device of which SCP 10 is one component.
MCPs were developed in order to allow electronic devices such as cellular telephone handsets to be made more compact than is possible using SCPs. FIG. 2 is a schematic plan view of the interior of an illustrative prior art MCP 30. Two integrated circuits 12A and 12B, each including respective pluralities of bonding pads 16, are fabricated on respective semiconductor dies 14A and 14B. Semiconductor dies 14A and 14B are mounted on a common substrate 18′ on which are formed electrically conductive traces 20′ connected to pins 22′. Most of the bonding pads 16 of integrated circuits 12A and 12B are electrically connected to respective traces 20′ by wire bonds 24. Some of the bonding pads 16 of integrated circuit 12A are electrically connected directly to bonding pads 16 of integrated circuit 12B by wire bonds 26. Alternatively, the bonding pads 16 of integrated circuits 12A and 12B that are connected to each other could be connected via wire bonds to traces, similar to traces 22′, on substrate 18′.
Prior art integrated circuits 12, 12A and 12B are designed on the assumption that bonding pads 16 are to be electrically connected to pins 22 by electrical circuitry such as wire bonds 24 and traces 20, without any intervening electronic components. These assumptions mandate the inclusion in integrated circuits 12, 12A and 12B of corresponding features such as electrostatic discharge protection and adequate input-output driver strength.